On April 24, local time in the United States, TSMC held the “2024 TSMC North America Technology Forum” in the United States, revealing its latest process technology, advanced packaging technology, and three-dimensional integrated circuit (3D IC) technology. With this leading semiconductor technology, Driving the next generation of artificial intelligence (AI) innovation.
It is understood that TSMC, in this North American technology forum,TSMC A16 (1.6nm) technology was disclosed for the first time, combining leading nanosheet transistors and innovative backside power rail solutions to significantly improve logic density and performance. Mass production is expected in 2026.
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TSMC also launched system-level wafer (TSMC-SoWTM) technology. This innovative solution brings revolutionary wafer-level performance advantages to meet the future AI requirements of ultra-large-scale data centers.
TSMC pointed out that it coincides with the 30th anniversary of the TSMC North America Technology Forum. The number of distinguished guests attending has increased from less than 100 30 years ago to more than 2,000 this year.
The North American Technology Forum was held in Santa Clara, California, USA, kicking off the global technology forums that will be launched in the next few months. This technology forum also has an innovation area to showcase the technological achievements of emerging customers.
TSMC President Dr. Wei Zhejia pointed out that we are in an AI-empowered world, where artificial intelligence functions are not only built in data centers, but also built into personal computers, mobile devices, cars, and even the Internet of Things.
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TSMC provides customers with the most complete technologies, from the world's most advanced silicon chips, to the widest range of advanced packaging portfolios and 3D IC platforms, to special process technologies that connect the digital world and the real world to realize their vision for AI. Vision.
New technologies announced at this forum include:
TSMC A16 Technology
As TSMC’s industry-leading N3E technology enters mass production,The next N2 technology is expected to be mass-produced in the second half of 2025.TSMC has launched new technology A16 on its technology roadmap.
According to reports, A16 will combine TSMC’s Super PowerRail architecture and nanosheet transistors, and is expected to be mass-produced in 2026.
This super rail technology moves the power supply network to the back of the wafer, freeing up more layout space for signal networks on the front of the wafer, thereby improving logic density and performance, making the A16 suitable for high-performance applications with complex signal wiring and dense power supply networks. computing (HPC) products.
TSMC stated,Compared with the N2P process, A16 is 8-10% faster at the same Vdd (working voltage), reduces power consumption by 15-20% at the same speed, and increases chip density by up to 1.10 times to support data center products.
TSMC’s innovative NanoFlex technology enables nanosheet transistors
TSMC’s upcoming N2 technology will be paired with TSMC NanoFlex technology, demonstrating TSMC’s new breakthrough in collaborative optimization of design technology.
TSMC NanoFlex provides chip designers with flexible N2 standard componentswhich are the basic building blocks of chip design, with lower components saving area and being more power efficient, while taller components maximize performance.
Customers can optimize the mix of high and low components within the same design memory block, adjusting the design to achieve the best balance between power, performance and area for their application.
N4C technology
TSMC also announced that it will launch advanced N4C technology to cater for a wider range of applications.
N4C continues N4P technology, reducing die costs by up to 8.5% and having a low adoption threshold. It is expected to be mass-produced in 2025.
According to reports, N4C provides area-effective basic silicon IP and design rules, which are fully compatible with the widely adopted N4P. Therefore, customers can easily migrate to N4C. The reduction in die size also improves the yield, emphasizing value. products provide a cost-effective option to upgrade to TSMC's next advanced technology.
CoWoS, system-on-chip, and system-on-wafer (TSMC-SoW)
TSMC’s CoWoS is a key enabling technology for the AI revolution, allowing customers to place more processor cores and high-bandwidth memory (HBM) side by side on a single interposer layer.
At the same time, TSMC’s System Integration Chip (SoIC) has become the leading solution for 3D chip stacking, and customers are increasingly adopting CoWoS with SoIC and other components to achieve the final System in Package (SiP) integration. .
TSMC’s system-level wafer technology provides an innovative option that allows 12-inch wafers to accommodate a large number of dies, provide more computing power, significantly reduce the space used in data centers, and improve performance per watt by several orders of magnitude.
TSMC’s first SoW product that has been mass-produced uses integrated fan-out (InFO) technology based on logic chips.The chip stack version using CoWoS technology is expected to be ready in 2027which can integrate SoIC, HBM and other components to create a wafer-level system that is powerful and has computing power comparable to a data center server rack or even an entire server.
Silicon Photonics Integration
TSMC is developing Compact Universal Photon Engine (COUPE) technology to support the explosive growth of data transmission brought about by the AI boom.
COUPE uses SoIC-X chip stacking technology to stack electronic dies on photonic dies. Compared with traditional stacking methods, it can provide the lowest resistance and higher energy efficiency for the die-to-die interface.
TSMC plans to complete COUPE verification supporting small plug-in connectors in 2025, and then integrate CoWoS packaging into co-packaged optics (CPO) in 2026, introducing optical connections directly into the package.
Advanced packaging for automotive
Following the launch of the N3AE process in 2023 to support early adoption by automotive customers, TSMC continues to meet automotive customers' needs for higher computing power by integrating advanced chips and packaging to meet driving safety and quality requirements.
TSMC is developing InFO-oS and CoWoS-R solutions to support applications such as advanced driver assistance systems (ADAS), vehicle control and central control computers. It is expected to complete AEC-Q100 second level verification in the fourth quarter of 2025.
Editor in charge: Shang Shangwen Q