According to news from Gamingdeputy on May 28, Ni Guangnan, an academician of the Chinese Academy of Engineering, once pointed out that the current CPU market is mainly monopolized by x86 and ARM architectures.And China wants to break this situation and realize self-control. The open source RISC-V architecture will be a great opportunity and development direction.
At the “RISC-V Open Source Processor Chip Ecological Development Forum” held yesterday, the second-generation “Xiangshan” (Nanhu architecture) open source high-performance RISC-V processor core was officially released. According to reports, “Xiangshan” will start engineering optimization in June 2022, and the development will be completed in September of the same year.It is planned to be taped out in June 2023, and its performance exceeds the Cortex-A76 released by ARM in 2018. The main frequency is 2GHz@14nm, and the SPEC 2006 score is 20 points.
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Xiangshan uses lakes to name each generation of architecture – the first generation architecture is Yanqi Lake, the second generation architecture is Nanhu Lake, and the third generation architecture is Kunming Lake. According to the Xiangshan Open Source Community, the first-generation “Yanqi Lake” architecture has been successfully taped out.Measured to achieve expected performancethe second-generation “Nanhu” architecture is being continuously iteratively optimized.
On August 24 last year, the Institute of Computing Technology of the Chinese Academy of Sciences, Beijing Open Source Chip Research Institute, Tencent, Alibaba, ZTE, Thundersoft, Yisiwei, and Suaneng formed a joint R&D team.Carry out the joint development of the third generation of Fragrant Hills (Kunming Lake Architecture).
The official also revealed that a number of enterprises in my country are developing high-end chips based on “Xiangshan”, such as AI chips, server chips, GPUs, etc., and are expected to make collective breakthroughs in 2025. Bao Yungang said that by then, Chinese companies are expected to gain a leading edge in the global RISC-V new ecology, open up the domestic and foreign dual cycles in the chip field, and realize the self-reliance and self-reliance of my country’s high-end processor chip industry.
Gamingdeputy inquired and learned that Xiangshan is an open source RISC-V processor core, implemented based on the Chisel hardware design language, and supports the RV64GC instruction set.
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“Nanhu” is manufactured using SMIC’s 14nm process, and the target frequency is 2GHzSPECCPU score reaches 10 points/GHz, supports dual-channel DDR memory and more functions such as PCIe, USB, HDMI, etc.
According to reports, “Xiangshan” is currently the highest-performance open source RISC-V processor core in the world. At present, the “Xiangshan” classic core and “Xiangshan” high-performance core “two-core” development goals have been determined.
The classic core is based on the second-generation “Xiangshan” engineering optimization, benchmarking against ARM A76, and provides CPU IP cores for industrial control, automobile, communication and other pan-industrial fields; the high-performance core is based on the performance of the third-generation “Xiangshan” (Kunming Lake) Upgrade, benchmark ARM N2, and provide high-performance CPU IP cores for data centers and computing power facilities.
One of the important decisions in the development of the “Xiangshan” processor core is to choose Chisel, an agile design language, because the development efficiency is much higher than that of Verilog, and to achieve the same function, the code volume of Chisel is only 1/5 of that of Verilog.