Gamingdeputy reported on January 7 that chip giant Intel recently received the industry's first ASML extreme ultraviolet (EUV) lithography machine with 0.55 numerical aperture (High-NA), which will help Intel achieve more advanced chips in the next few years. Process. In sharp contrast, another giant, TSMC, is standing still and seems to be in no rush to join the race for next-generation lithography technology. Industry analysts predict that TSMC may not adopt this technology until 2030 or even later.
The High-NA EUV lithography machine Intel acquired this time will first be used to learn and master this technology, and is expected to be used in chip process nodes after 18A (1.8nm process) in the next two to three years. In contrast, TSMC has adopted a more cautious strategy. Analysts from China Renaissance and SemiAnalysis believe that,TSMC may not adopt High-NA EUV technology until after the N1.4 process (expected to be after 2030).
Analyst Szeho Ng said: “Unlike Intel's plan to introduce High-NA EUV and GAA transistors into the 20A process at the same time, we expect TSMC to introduce High-NA EUV after the N1.4 process, and not until after 2030 at the earliest.”
Gamingdeputy noted that Intel’s radical process roadmap includes the introduction of RibbonFET full-gate transistors and PowerVia back-side power supply networks starting from 20A (2nm level), then further optimizing at 18A, and adopting High-NA EUV lithography at nodes after 18A. machine to achieve lower power consumption, higher performance and smaller chip size.
The current mainstream EUV lithography machine uses a 0.33 numerical aperture (Low-NA) lens, which can achieve critical dimensions of 13 to 16 nanometers in mass production, which is enough to produce 26 nanometer metal spacing and 25 to 30 nanometer interconnect spacing. This is enough for the 3nm level process, but with the shrinkage of the process, the metal spacing will shrink to 18-21 nanometers (imec data), which will require EUV double exposure, patterned etching or High-NA single exposure and other technologies .
Intel plans to introduce patterned etching starting from 20A, and then adopt High-NA EUV at nodes after 18A, which can reduce the complexity of the process flow and avoid the use of EUV double exposure. However, High-NA EUV lithography machines are much more expensive than Low-NA EUV lithography machines, and they also have a series of special features such as reducing the exposure area by half.
Analysts believe that, at least initially, the cost of High-NA EUV may be higher than that of Low-NA EUV double exposure, which is why TSMC is temporarily waiting and watching.TSMC prefers to use mature technologies with lower costs to ensure product competitiveness.
“Although Low-NA EUV multiple exposures will reduce production capacity, its cost may still be lower than High-NA EUV,” explained China Renaissance analyst Szeho Ng. “High-NA EUV requires higher light source power to drive finer critical size, which accelerates wear of the projection optics and reticle, negating the advantages of higher throughput. This is consistent with TSMC's strategy of targeting the mass market with the most cost-competitive technology.”
TSMC began using EUV lithography machines in chip mass production as early as 2019, a few months later than Samsung and a few years earlier than Intel. Intel hopes to get ahead of Samsung and TSMC in the High-NA EUV field and gain certain technical and strategic advantages. If TSMC waits until 2030 or later to adopt High-NA EUV, can it maintain its leading position in chip manufacturing technology?